Design of FIR filter with Fast Adders and Fast Multipliers using RNS Algorithm

Author:

M Balaji1,N Padmaja1,P Gitanjali2,Shaik Saif Ali2,P Siva Kumar2,R Sai Geetesh2

Affiliation:

1. Mohan Babu University,Dept. of ECE,Tirupathi,India

2. Sree Vidyanikethan Engg. College,Dept. of ECE,Tirupathi,India

Publisher

IEEE

Reference15 articles.

1. Design of PLC based Building Control for Energy Optimization

2. Modified High-Speed FIR Filter Using DA-RNS Architecture;khan;International Journal of Advanced Science and Technology,2020

3. Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications

4. 521 Lecture Notes in Electrical Engineering ASIC Implementation of Low Power, Area Efficient Adaptive FIR Filter Using Pipelined DA;naga jyothi,2019

5. Smart Monitoring System for Waste Management Using IoT

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1. Design and Evaluation of 32-Bit N-Tap FIR Filter for Audio Processing Applications;2024 1st International Conference on Innovative Sustainable Technologies for Energy, Mechatronics, and Smart Systems (ISTEMS);2024-04-26

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3. RNS based FIR filter design with memory less distributed arithmetic filtering for high speed and low power applications;AIP Conference Proceedings;2024

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