Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines-Reference-Cited by-同舟云学术

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Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines

Published:2008-09 Issue: Volume: Page:
ISSN:
Container-title:2008 IEEE Custom Integrated Circuits Conference
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Author:

Arslan Umut,McCartney Mark P.,Bhargava Mudit,Xin Li ,Ken Mai ,Pileggi Lawrence T.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4665385/4671999/04672108.pdf?arnumber=4672108

Cited by 18 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of High-Speed, Low-Power Sensing Circuits for Nano-Scale Embedded Memory;Sensors;2023-12-19

2. Analysis of SRAM Enhancements Through Sense Amplifier Capacitive Offset Correction and Replica Self-Timing;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-06

3. A Reconfigurable Replica Bitline to Determine Optimum SRAM Sense Amplifier Set Time;Proceedings of the on Great Lakes Symposium on VLSI 2017;2017-05-10

4. A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process;IEEE Journal of Solid-State Circuits;2017-03

5. A Variation-Tolerant Replica-Based Reference-Generation Technique for Single-Ended Sensing in Wide Voltage-Range SRAMs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2016-05

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