Analysis of SRAM Enhancements Through Sense Amplifier Capacitive Offset Correction and Replica Self-Timing-Reference-Cited by-同舟云学术

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Analysis of SRAM Enhancements Through Sense Amplifier Capacitive Offset Correction and Replica Self-Timing

Published:2019-06 Issue:6 Volume:66 Page:2037-2050
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Fragasse Roman^ORCID,Tantawy Ramy^ORCID,Dupaix Brian^ORCID,Dean Trevor^ORCID,Disabato Daron,Belz Matthew R.^ORCID,Smith Dale,Mccue Jamin^ORCID,Khalil Waleed

Funder

Air Force Research Laboratory

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/8715688/08698826.pdf?arnumber=8698826

Cited by 19 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of High-Speed, Low-Power Sensing Circuits for Nano-Scale Embedded Memory;Sensors;2023-12-19

2. Modified Decoupled Sense Amplifier with Improved Sensing Speed for Low-Voltage Differential SRAM;ACM Transactions on Design Automation of Electronic Systems;2023-10-16

3. Cross-Coupled nFET Preamplifier for Low Voltage SRAM;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-09

4. A Single-Ended Offset-Canceling Sense Amplifier Enabling Wide-Voltage Operations;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-03

5. CharTM: The dynamic stability characterization for memory based on tail distribution modeling;Microelectronics Journal;2023-03

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