THRAM: A Template-based Heterogeneous CGRA Modeling Framework Supporting Fast DSE

Author:

Li Jingyuan1,Qiu Yunhui1,Zhu Guowei1,Zhu Qilong1,Yin Wenbo1,Wang Lingli1

Affiliation:

1. Fudan University,State Key Lab of ASIC and System,Shanghai,China

Publisher

IEEE

Reference30 articles.

1. Snafu: An Ultra-Low-Power, Energy-Minimal CGRA-Generation Framework and Architecture

2. OpenCGRA: Democratizing Coarse-Grained Recon-figurable Arrays;tan;2021 IEEE 32nd International Conference on Application-specific Systems Architectures and Processors (ASAP),2021

3. Formulating Data-arrival Synchronizers in Integer Linear Programming for CGRA Mapping

4. DSAGEN: Synthesizing Programmable Spatial Accelerators;weng;2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA),2020

5. Hebo: Heteroscedastic evolutionary bayesian optimisation;cowen-rivers;ArXiv Preprint,2020

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2. HierCGRA: A Novel Framework for Large-scale CGRA with Hierarchical Modeling and Automated Design Space Exploration;ACM Transactions on Reconfigurable Technology and Systems;2024-05-10

3. CDE: A Novel CGRA Development Environment with Fast Design Space Exploration Framework;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

4. An Agile Deploying Approach for Large-Scale Workloads on CGRA-CPU Architecture;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25

5. AUGER: A Multi-Objective Design Space Exploration Framework for CGRAs;2023 International Conference on Field Programmable Technology (ICFPT);2023-12-12

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