Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling-Reference-Cited by-同舟云学术

Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling

Published:2020-12 Issue:12 Volume:67 Page:5349-5354
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Gupta Anshul^ORCID,Pedreira Olalla Varela,Arutchelvan Goutham,Zahedmanesh Houman,Devriendt Katia^ORCID,Mertens Hans,Tao Zheng^ORCID,Ritzenthaler Romain^ORCID,Wang Shouhua,Radisic Dunja,Kenis Karine,Teugels Lieve,Sebai Farid,Lorant Christophe^ORCID,Jourdan Nicolas,Chan Boon Teik,Subramanian Sujith,Schleicher Filip^ORCID,Hopf Toby,Peter Antony Premkumar,Rassoul Nouredine,Debruyn Haroen,Demonie Ingrid,Siew Yong Kong,Chiarella Thomas,Briggs Basoene,Zhou Xiuju^ORCID,Rosseel Erik,De Keersgieter An^ORCID,Capogreco Elena^ORCID,Litta Eugenio Dentoni^ORCID,Boccardi Guillaume,Baudot Sylvain,Mannaert Geert,Bontemps Noemie,Sepulveda A.^ORCID,Mertens Sofie,Kim Min-Soo,Dupuy Emmanuel,Vandersmissen Kevin,Paolillo Sara,Yakimets Dmitry^ORCID,Chehab Bilal,Favia Paola,Drijbooms Christel,Cousserier Joris,Jaysankar Manoj^ORCID,Lazzarino Frederic,Morin Pierre,Altamirano Efrain,Mitard Jerome,Wilson Christopher J.,Holsteyns Frank,Boemmels Juergen^ORCID,Demuynck Steven,Tokei Zsolt,Horiguchi Naoto

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/9269285/09257401.pdf?arnumber=9257401

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