High-density standard cell libraries with backside power options in A14 nanosheet node-Reference-Cited by-同舟云学术

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High-density standard cell libraries with backside power options in A14 nanosheet node

Published:2024-04-10 Issue: Volume: Page:8
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Container-title:DTCO and Computational Patterning III
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Author:

Kukner Halil,Mirabelli Gioele,Yang Sheng,Zhou Yun,Makarov Alexander,Xiang Yang,Boemmels Juergen,Veloso Anabela,Zografos Odysseas,Weckx Pieter,Ryckaert Julien,Hellings Geert

Publisher

SPIE

Reference15 articles.

1. Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires

2. Enabling cmos scaling towards 3nm and beyond;Mocuta,2018

3. Nano-through silicon vias (ntsv) for backside power delivery networks (bspdn);Beyne,2023

4. A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes

5. Extending the roadmap beyond 3nm through system scaling boosters: A case study on Buried Power Rail and Backside Power Delivery

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