Interconnect Scheme for Die-to-Die and Die-to-Wafer-Level Heterogeneous Integration for High-Performance Computing-Reference-Cited by-同舟云学术

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Interconnect Scheme for Die-to-Die and Die-to-Wafer-Level Heterogeneous Integration for High-Performance Computing

Published:2019-05 Issue: Volume: Page:
ISSN:
Container-title:2019 IEEE 69th Electronic Components and Technology Conference (ECTC)
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Author:

Das Rabindra,Bolkhovsky Vladimir,Galbraith Christopher,Oates Daniel,Plant Jason,Lambert Renee,Zarr Scott,Rastogi Ravi,Shapiro Dmitri,Docanto Manuel,Weir Terence,Johnson Leonard

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8795274/8811008/08811062.pdf?arnumber=8811062

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Formation of 10 µm Pitch Sharp Micro-Bump by Fusion Process of Imprint and Photolithography;2024 International Conference on Electronics Packaging (ICEP);2024-04-17

2. Extremely large area (88 mm × 88 mm) superconducting integrated circuit (ELASIC);Scientific Reports;2023-07-21

3. Characterizations of Indium Interconnects for 3D Quantum Assemblies;2023 IEEE 73rd Electronic Components and Technology Conference (ECTC);2023-05

4. Demonstration of 90 000 superconductive bump connections for massive quantum computing;Japanese Journal of Applied Physics;2023-03-15

5. Nb–Nb direct bonding at room temperature for superconducting interconnects;Journal of Applied Physics;2023-01-06

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