Author:
Araga Yuuki,Nakagawa Hiroshi,Hashino Masaru,Kikuchi Katsuya
Abstract
Abstract
We developed fabrication and bonding technology of superconductive bump for massive quantum computing. A bonded test vehicle demonstrates supercurrent through 90 000 series daisy-chain. Proposed bump consists of lead-indium alloy. The bumps land onto gold pad on the opposite chip and alloy with the gold pad for supercurrent. The primary advantage of the proposed bump is the minimized damage to the quantum chip. Plasma cleaning process which may degrade sensitive components is only required for bump chips and not for quantum chips. Lower bonding temperature of 100 degrees Celsius for the proposed bump also keeps sensitive components away from degradation in high temperature.
Subject
General Physics and Astronomy,General Engineering
Cited by
2 articles.
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1. Integration Technology for Superconducting Quantum Circuits;2024 IEEE Silicon Nanoelectronics Workshop (SNW);2024-06-15
2. R&D of 3D-IC Technology for System Integration;Journal of The Japan Institute of Electronics Packaging;2023-07-01