Author:
Gadakh Sheetal N.,Khade Amitkumar
Cited by
8 articles.
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1. 16-bit Vedic multiplier Using Carry Skip Adder;2024 International Conference on Intelligent Systems for Cybersecurity (ISCS);2024-05-03
2. FPGA Implementation of DFT Processor using Vedic Multiplier;International Journal of Advanced Research in Science, Communication and Technology;2024-01-31
3. Design and Analysis of 8-bit Vedic Multiplier;2023 5th Biennial International Conference on Nascent Technologies in Engineering (ICNTE);2023-01-20
4. PPA Based MAC Unit Using Vedic Multiplier and XOR Logic;Communications in Computer and Information Science;2023
5. Design of 16-Bit Vedic Multiplier Using Modified Logic Gates and BEC Technique;Lecture Notes in Electrical Engineering;2022-09-04