Design of 16-Bit Vedic Multiplier Using Modified Logic Gates and BEC Technique
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-19-0312-0_8
Reference11 articles.
1. Bathija RK, Meena RS, Sarkar S (2012) Low power high speed 16*16-bit multiplier using Vedic mathematics. Int J Comput Appl
2. Jie LS, Rusian SH (2017) A 2x2 bit Vedic multiplier with different adders in 90nm CMOS technology. AIP Conf Proc 1883:020017
3. Gadakh SN, Khade A (2016) Design and optimization of 16×16 Bit multiplier using Vedic mathematics. In: 2016 international conference on automatic control and dynamic optimization techniques (ICACDOT). Pune, pp 460–464
4. Rao KD, Gangadhar C, Korrai PK (2016) FPGA implementation of complex multiplier using minimum delay Vedic real multiplier architecture. In: 2016 IEEE Uttar Pradesh section international conference on electrical, computer and electronics engineering (UPCON). Varanasi, pp 580–584
5. Natarajan PB, Ghosh S, Karthik R (2017) Low power high performance carry select adder, pp 601–603
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