A 2x2 bit Vedic multiplier with different adders in 90nm CMOS technology-Reference-Cited by-同舟云学术

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A 2x2 bit Vedic multiplier with different adders in 90nm CMOS technology

Published:2017 Issue: Volume: Page:
ISSN:0094-243X
Container-title:AIP Conference Proceedings
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Author:

Jie Lee Shing,Ruslan Siti Hawa

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Link

http://aip.scitation.org/doi/pdf/10.1063/1.5002035

Reference22 articles.

1. D. Krishnaveni and T. G Umarani. Int. J. Adv. Technol. Eng. Res. 2, 10–14 (2012).

2. S. J. Lee and S. H. Ruslan. Int. J. Integr. Eng. 8, (2016).

3. “Mutipliers.” [Online]. Available: https://www.coursehero.com/file/12105364/L3-Notes/. [Accessed: 03-Dec-2016].

4. K. Linet, P. Umarani, and T. Ravi. Int. J. Adv. Res. Electr. Electron. Instrum. Eng. 3, 9417–9424 (2014).

5. J. Sharma and S. Kumar. Int. J. Sci. Res. 3, (2014).

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