A Low Voltage Steep Turn-Off Tunnel Transistor Design
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5290183/5290184/05290257.pdf?arnumber=5290257
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Z‐shaped gate TFET with horizontal pocket for improvement of electrostatic behavior;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2020-09-10
2. Heavy ion induced single-event-transient effects in nanoscale ferroelectric vertical tunneling transistors by TCAD simulation;Semiconductor Science and Technology;2020-08-31
3. Total ionization dose effects of N-type tunnel field effect transistor (TFET) with ultra-shallow pocket junction;Applied Physics A;2020-05-22
4. Design and analysis of high k silicon nanotube tunnel FET device;IET Circuits, Devices & Systems;2019-11
5. Simulation of planar single-gate Si tunnel FET with average subthreshold swing of less than 60 mV/decade for 0.3 V operation;Japanese Journal of Applied Physics;2018-03-06
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