Simulation of planar single-gate Si tunnel FET with average subthreshold swing of less than 60 mV/decade for 0.3 V operation-Reference-Cited by-同舟云学术

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Simulation of planar single-gate Si tunnel FET with average subthreshold swing of less than 60 mV/decade for 0.3 V operation

Published:2018-03-06 Issue:4S Volume:57 Page:04FD09
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:
Short-container-title:Jpn. J. Appl. Phys.

Author:

Kukita Kentaro,Uechi Tadayoshi,Shimokawa Junji,Goto Masakazu,Yokota Yoshinori,Kawanaka Shigeru,Tanamoto Tetsufumi,Tanimoto Hiroyoshi,Takagi Shinichi

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Link

http://stacks.iop.org/1347-4065/57/i=4S/a=04FD09/pdf

Reference34 articles.

1. Complementary tunneling transistor for low power application

2. 70-nm impact-ionization metal-oxide-semiconductor (I-MOS) devices integrated with tunneling field-effect transistors (TFETs)

3. Correction to "Revision of Tunneling Field-Effect Transistor in Standard CMOS Technologies"

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Architecture- and Gate-Oxide-Level Optimization of a Si-Based Asymmetric U-TFET for Low Power Operation: a Real-Time Gate/Drain Electrostatic Based Leakage Perspective;Silicon;2022-03-16

2. Modification of Bayesian Optimization for Efficient Calibration of Simulation Models;2020 Winter Simulation Conference (WSC);2020-12-14

3. SPICE simulation of 32-kHz crystal-oscillator operation based on Si tunnel FET;IEICE Electronics Express;2020

4. Investigation on the Effects of Gate-Source Overlap/Underlap and Source Doping Gradient of n-Type Si Cylindrical Gate-All-Around Tunnel Field-Effect Transistors;IEEE Transactions on Nanotechnology;2020

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