Utilization of Noise-Shaping in Mixed-Signal Timing-Skew Mismatch Calibration of TI-ADCs
Author:
Affiliation:
1. Polytechnique Montréal,Electrical Engineering Department,Montréal,Canada
2. Ciena Corporation,Analog IC Department,Ottawa,Canada
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10557746/10557828/10557896.pdf?arnumber=10557896
Reference11 articles.
1. Delay-Locked Loop Based Multiphase Clock Generator for Time-Interleaved ADCs
2. A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET
3. All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition
4. Background Calibration of Time-Interleaved ADCs with Polyphase Filters
5. A Novel Channel Randomization Method for Time-Interleaved ADCs
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