Background Calibration of Time-Interleaved ADCs with Polyphase Filters
Author:
Affiliation:
1. Polytechnique Montréal,Electrical Engineering Department,Montréal,Canada
2. Ciena Corporation,Ottawa,Canada
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10198027/10198028/10198094.pdf?arnumber=10198094
Reference22 articles.
1. Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS
2. An Energy-Efficient Hierarchical Architecture for Time-Interleaved SAR ADC
3. A 2-GS/s 8-bit Time-Interleaved SAR ADC for Millimeter-Wave Pulsed Radar Baseband SoC
4. A Foreground Calibration for M-Channel Time-Interleaved Analog-to-Digital Converters Based on Genetic Algorithm
5. Digital signal processing;oppenheim;Research supported by the Massachusetts Institute of Technology Bell Telephone Laboratories and Guggenheim Foundation,1975
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Utilization of Noise-Shaping in Mixed-Signal Timing-Skew Mismatch Calibration of TI-ADCs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. Digital Compensation of Timing Skew Mismatches in Time-Interleaved ADCs by Source Separation;IEEE Transactions on Instrumentation and Measurement;2024
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