Delay-Locked Loop Based Multiphase Clock Generator for Time-Interleaved ADCs-Reference-Cited by-同舟云学术

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Delay-Locked Loop Based Multiphase Clock Generator for Time-Interleaved ADCs

Published:2021-11-28 Issue: Volume: Page:
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Container-title:2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)
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Author:

Alhousseiny Ibrahim,Ali Mohamed,Ben-Hamida Naim,Honarparvar Mohammad,Sawan Mohamad,Savaria Yvon

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9665417/9665446/09665452.pdf?arnumber=9665452

Reference10 articles.

1. 56Gs/s ADC : Enabling 100GbE

2. A 3.6 pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS;yueksel;IEEE European Solid-State Circuits Conference,0

3. An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation

4. A low power frequency synthesizer for biosensor applications in the MedRadio band

5. Simple high‐resolution CMOS phase frequency detector

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Utilization of Noise-Shaping in Mixed-Signal Timing-Skew Mismatch Calibration of TI-ADCs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. A Wide-Range and High-Linearity Timing Generator with 1.25ps-Resolution;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20

3. 5 GHz Phase-Locked Loop With a Phase-Adjusting Function;IEEE Microwave and Wireless Technology Letters;2023-05

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