Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection

Author:

Cherupally Sai Kiran,Meng Jian,Rakin Adnan Siraj,Yin Shihui,Seok Mingoo,Fan Deliang,Seo Jae-sun

Funder

National Science Foundation

Semiconductor Research Corporation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Robustness Assessment Approach for Hardware Noise-Based Convolutional Neural Networks;2024 9th International Conference on Computer and Communication Systems (ICCCS);2024-04-19

2. Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures;IEEE Journal on Exploratory Solid-State Computational Devices and Circuits;2024

3. An Energy Efficient All-Digital Time-Domain Compute-in-Memory Macro Optimized for Binary Neural Networks;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-01

4. Scalable Time-Domain Compute-in-Memory BNN Engine with 2.06 POPS/W Energy Efficiency for Edge-AI Devices;Proceedings of the Great Lakes Symposium on VLSI 2023;2023-06-05

5. PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference;IEEE Journal of Solid-State Circuits;2023-05

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