Scalable Time-Domain Compute-in-Memory BNN Engine with 2.06 POPS/W Energy Efficiency for Edge-AI Devices

Author:

Lou Jie1ORCID,Freye Florian1ORCID,Lanius Christian1ORCID,Gemmeke Tobias1ORCID

Affiliation:

1. RWTH Aachen University, Aachen, Germany

Funder

Federal Ministry of Education and Research (BMBF, Germany) NEUROTEC II Project

Publisher

ACM

Reference26 articles.

1. A Time-Domain Computing Accelerated Image Recognition Processor With Efficient Time Encoding and Non-Linear Logic Operation

2. Zhengyu Chen et al. 2020. A Mixed-signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixedsignal On-chip Training for Low Power Edge Devices . In IEEE Symp. on VLSI Circuits. https://doi.org/10 .1109/VLSICircuits 1822 2.2020.9162829 10.1109/VLSICircuits18222.2020.9162829 Zhengyu Chen et al. 2020. A Mixed-signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixedsignal On-chip Training for Low Power Edge Devices. In IEEE Symp. on VLSI Circuits. https://doi.org/10.1109/VLSICircuits18222.2020.9162829

3. Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection

4. Yu-Der Chih et al. 2021. An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAMBased Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications . In IEEE Int. Solid-State Circuits Conf. (ISSCC). 252--253 . https: //doi.org/10.1109/ISSCC42613. 2021 .9365766 10.1109/ISSCC42613.2021.9365766 Yu-Der Chih et al. 2021. An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAMBased Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications. In IEEE Int. Solid-State Circuits Conf. (ISSCC). 252--253. https: //doi.org/10.1109/ISSCC42613.2021.9365766

5. An Energy-Efficient One-Shot Time-Based Neural Network Accelerator Employing Dynamic Threshold Error Correction in 65 nm

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