PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference-Reference-Cited by-同舟云学术

PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference

Published:2023-05 Issue:5 Volume:58 Page:1436-1449
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Zhang Bo¹^ORCID,Yin Shihui²^ORCID,Kim Minkyu²^ORCID,Saikia Jyotishman²,Kwon Soonwan³^ORCID,Myung Sungmeen³,Kim Hyunsoo³,Kim Sang Joon³^ORCID,Seo Jae-Sun²^ORCID,Seok Mingoo¹^ORCID

Affiliation:

1. Department of Electrical Engineering, Columbia University, New York, NY, USA

2. School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA

3. Samsung Advanced Institute of Technology, Suwon, South Korea

Funder

Samsung Electronics

Center for Brain-inspired Computing (C-BRIC), one of six centers in Joint University Microelectronics Program (JUMP), an Semiconductor Research Corporation (SRC) Program

Defense Advanced Research Projects Agency

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10107667/09923750.pdf?arnumber=9923750

Reference34 articles.

1. A 65 nm 4 Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8 TOPS/W fully parallel product-sum operation for binary DNN edge processors;khwa;Proc IEEE Int Solid State Circuits Conf (ISSCC),2018

2. An In-Memory VLSI Architecture for Convolutional Neural Networks

3. Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection

4. 15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips

5. A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors

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