A BIST scheme for on-chip ADC and DAC testing

Author:

Jiun-Lang Huang ,Chee-Kian Ong ,Kwang-Ting Cheng

Publisher

IEEE Comput. Soc

Cited by 22 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design and Implementation of ADCBIST for Dynamic Parameter Measurement;2024 1st International Conference on Innovative Sustainable Technologies for Energy, Mechatronics, and Smart Systems (ISTEMS);2024-04-26

2. An On Chip BIST Architecture for ADC Parameter Testing and Measurement;2024 1st International Conference on Innovative Sustainable Technologies for Energy, Mechatronics, and Smart Systems (ISTEMS);2024-04-26

3. An Efficient Time-Tick based BIST Scheme to Calculate Static Errors of ADC;2023 International Conference on Intelligent Technologies for Sustainable Electric and Communications Systems (iTech SECOM);2023-12-18

4. Implementation of Linear Test Stimulus Generator for Non-linearity Computation of ADC;Instruments and Experimental Techniques;2023-08

5. Analysis of Non-Idealities in On-Chip Loopback Testing of Data Converters;2023 IEEE International Test Conference India (ITC India);2023-07-23

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