CATS: Cycle Accurate Transaction-driven Simulation with Multiple Processor Simulators
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/4211748/4211749/04211890.pdf?arnumber=4211890
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2. A leakage-aware L2 cache management technique for producer–consumer sharing in low-power chip multiprocessors;Journal of Parallel and Distributed Computing;2011-12
3. WCET analysis of modern processors using multi-criteria optimisation;Empirical Software Engineering;2010-06-08
4. Reusability-aware cache memory sharing for chip multiprocessors with private L2 caches;Journal of Systems Architecture;2009-10
5. Broadcast filtering: Snoop energy reduction in shared bus-based low-power MPSoCs;Journal of Systems Architecture;2009-03
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