Author:
Kunhyuk Kang ,Paul B.C.,Roy K.
Cited by
5 articles.
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1. NN-SSTA: A deep neural network approach for statistical static timing analysis;Expert Systems with Applications;2020-07
2. Path Delay Under Process Variations;Timing Performance of Nanometer Digital Circuits Under Process Variations;2018
3. Gate Delay Under Process Variations;Timing Performance of Nanometer Digital Circuits Under Process Variations;2018
4. Low VDD and body bias conditions for testing bridge defects in the presence of process variations;Microelectronics Journal;2015-05
5. Low-Power Design Techniques and Test Implications;Power-Aware Testing and Test Strategies for Low Power Devices;2009-08-13