16.2 A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input-Reference-Cited by-同舟云学术

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16.2 A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input

Published:2020-02 Issue: Volume: Page:
ISSN:
Container-title:2020 IEEE International Solid- State Circuits Conference - (ISSCC)
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Author:

Zhang Minglei,Zhu Yan,Chan Chi-Hang,Martins Rui P.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9046640/9062887/09062986.pdf?arnumber=9062986

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. The Race for the Extra Pico Second without Losing the Decibel: A Partial-Review of Single-Channel Energy-Efficient High-Speed Nyquist ADCs;2024 IEEE Custom Integrated Circuits Conference (CICC);2024-04-21

2. A 5GS/s 38.04dB SNDR Single-Channel TDC-Assisted Hybrid ADC with $\lambda/4$ Transmission Line Based Time Quantizer Achieving a PVT Robustness 416.6fs Time Step;2023 IEEE Asian Solid-State Circuits Conference (A-SSCC);2023-11-05

3. Scalable Coherent Optical Crossbar Architecture using PCM for AI Acceleration;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04

4. A 1.9-ps 8× phase interpolation TDC for time-based analog-to-digital converter with capacitance compensation self-calibration;IEICE Electronics Express;2023-02-10

5. Hybrid Timing Error Detector for Baud Rate Multilevel Clock and Data Recovery;IEEE Open Journal of Circuits and Systems;2023

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