A 5GS/s 38.04dB SNDR Single-Channel TDC-Assisted Hybrid ADC with $\lambda/4$ Transmission Line Based Time Quantizer Achieving a PVT Robustness 416.6fs Time Step-Reference-Cited by-同舟云学术

A 5GS/s 38.04dB SNDR Single-Channel TDC-Assisted Hybrid ADC with $\lambda/4$ Transmission Line Based Time Quantizer Achieving a PVT Robustness 416.6fs Time Step

Published:2023-11-05 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE Asian Solid-State Circuits Conference (A-SSCC)
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Author:

Liang Hongzhi¹,Shen Yi¹,Chang Jun¹,Liu Shubin¹,Ding Ruixue¹,Zhu Zhangming¹

Affiliation:

1. School of Microelectronics, Xidian University,Key Laboratory of Analog Integrated Circuits and Systems, (Ministry of Education),Xi'an,China

Funder

National Key R&D Program of China

National Natural Science Foundation of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10347557/10347908/10347964.pdf?arnumber=10347964

Reference7 articles.

1. A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS

2. 16.2 A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input

3. A 10GS/s 8b 25fJ/c-s 2850um² Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology

4. A 2-way 7.3-bit 10 GS/s Time-based Folding ADC with Passive Pulse-Shrinking Cells

5. 13.5 Standing Wave Based Clock Distribution Technique with Application to a $10\times 11$ Gbps Transceiver in 28 nm CMOS;Li,2015

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