Demonstration of L-Channel Tunnel FET with Triple Metal Gate for Next Generation IC Technology
Author:
Affiliation:
1. VIT-AP University,School of Electronics Engineering.,Amaravati,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10134757/10134565/10134918.pdf?arnumber=10134918
Reference20 articles.
1. Effect of asymmetric gate–drain overlap on ambipolar behavior of double-gate TFET and its impact on HF performances
2. Asymmetric gating for reducing leakage current in carbon nanotube field-effect transistors
3. Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications
4. Reduction of TFET OFF-Current and Subthreshold Swing by Lightly Doped Drain
5. Source Extended GaSb/GaAs Heterojunction GAATFET to Improve ION/IOFF Ratio
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