Design and Evaluation of a Face-Down Embedded SiC Power Module With Low Parasitic Inductance and Low Thermal Resistance
Author:
Affiliation:
1. Department of Applied Electronics, Zhejiang University, Hangzhou, China
2. Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China
Funder
National Natural Science Foundation of China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/63/9998566/09920223.pdf?arnumber=9920223
Reference15 articles.
1. 400 A, 1200 V SiC power module with 1nH commutation inductance;beckedahl;Proc 9th Int Conf Integr Power Electron Syst,2016
2. A Solution to Press-Pack Packaging of SiC MOSFETS
3. Fan-Out Panel-Level PCB-Embedded SiC Power MOSFETs Packaging
4. Development of an ultra-high density Power Chip on Bus (PCoB) module
5. A Comparative Study on Reliability and Ruggedness of Kelvin and Non-Kelvin Packaged SiC Mosfets
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1. Innovative Reverse Current Coupling Layout of SiC Power Module for Parasitic Inductance Reduction;IEEE Transactions on Electron Devices;2024-09
2. Substrate Embedded Power Electronics Packaging for Silicon Carbide mosfets;IEEE Transactions on Power Electronics;2024-08
3. A Fourier Series-Based Steady-State Thermal Resistance Model for Power Module;IEEE Journal of Emerging and Selected Topics in Power Electronics;2024-08
4. Design and Demonstration of 3D-Stacked Packaging SiC Power Module with Low Parasitic Inductance and Low Thermal Resistance;2023 IEEE 2nd International Power Electronics and Application Symposium (PEAS);2023-11-10
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