Design and Demonstration of 3D-Stacked Packaging SiC Power Module with Low Parasitic Inductance and Low Thermal Resistance-Reference-Cited by-同舟云学术

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Design and Demonstration of 3D-Stacked Packaging SiC Power Module with Low Parasitic Inductance and Low Thermal Resistance

Published:2023-11-10 Issue: Volume: Page:1715-1719
ISSN:
Container-title:2023 IEEE 2nd International Power Electronics and Application Symposium (PEAS)
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Author:

Liang Senhao¹,Liang Yuxi¹,Sun Peng¹,Gong Jiakun¹,Zou Mingrui¹,Zeng Zheng¹

Affiliation:

1. School of Electrical Engineering, Chongqing University,State Key Laboratory of Power Transmission Equipment Technology,Chongqing,China,400044

Funder

National Natural Science Foundation of China

Chongqing Research Program of Basic Research and Frontier Technology

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10394673/10394683/10394781.pdf?arnumber=10394781

Reference15 articles.

1. An Advanced Power Electronics Interface for Electric Vehicles Applications

2. Improving the Overall Efficiency of Automotive Inverters Using a Multilevel Converter Composed of Low Voltage Si mosfets

3. A Novel SiC-Based Multifunctional Onboard Battery Charger for Plug-In Electric Vehicles

4. Stepwise Design Methodology and Heterogeneous Integration Routine of Air-Cooled SiC Inverter for Electric Vehicle

5. Analysis and Suppression of Shaft Voltage in SiC-Based Inverter for Electric Vehicle Applications

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