Layout-Dominated Dynamic Current Balancing Analysis of Multichip SiC Power Modules Based on Coupled Parasitic Network Model
Author:
Affiliation:
1. School of Electrical and Electronic Engineering, Huazhong University of Science and Technology, Wuhan, China
Funder
National Natural Science Foundation of China
Hubei Jiufengshan Laboratory
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/63/9952160/09895323.pdf?arnumber=9895323
Reference27 articles.
1. EM-Electrothermal Analysis of Semiconductor Power Modules
2. Paralleling of chips—From worst-case scenario to a statistical approach;scheuermann;EngineerIT,2008
3. A Double-End Sourced Wire-Bonded Multichip SiC MOSFET Power Module With Improved Dynamic Current Sharing
4. A Novel DBC Layout for Current Imbalance Mitigation in SiC MOSFET Multichip Power Modules
5. Layout-Dominated Dynamic Imbalanced Current Analysis and Its Suppression Strategy of Parallel SiC MOSFETs
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1. A Dynamic Current Balancing Method for Paralleled SiC MOSFETs With Gate-Branch Full-Coupled Inductors;IEEE Transactions on Power Electronics;2024-10
2. Innovative Reverse Current Coupling Layout of SiC Power Module for Parasitic Inductance Reduction;IEEE Transactions on Electron Devices;2024-09
3. A Dynamic Current Sharing Model of Multichip Parallel SiC MOSFETs Considering Layout-Dominated Mutual Inductance Coupling;IEEE Transactions on Power Electronics;2024-09
4. Dynamic Current Sharing Mechanism Analysis of Paralleled SiC MOSFETs Considering Parasitic Mutual Inductances Based on an Improved Model;IEEE Transactions on Power Electronics;2024-06
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