1. Comparison and Performance Analysis of Various Low Power Digital Design Techniques;buch;International Journal of Applied Engineering Research,2018
2. Single bit line accessed high‐performance ultra‐low voltage operating 7T static random access memory cell with improved read stability
3. Design of CMOS inverter using lector technique to reduce the leakage power;gaonkar;International Journal of Technical Research and Applications,2015
4. Ultra-low power VLSI design;raju,2018
5. Comparative Analysis Of Cmos Inverter For Low Leakage Power;kumre;International Journal of Scientific & Technology Research,2019