Author:
Zhijun Huang ,Ercegovac M.D.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software
Cited by
58 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Systematic exploration of N-bit Vedic multipliers: A roadmap of technological approaches in pursuit of future trends;Nano Communication Networks;2024-12
2. Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-07
3. A Two-Speed,Radix-4, Parallel-Parallel Multiplier;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28
4. A Low-Complexity Design for Complex Multiplication Using Radix-4 Booth Encoding;2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA);2024-05-17
5. Design of Efficient Matrix Multiplication Processing Elements in Systolic Arrays using Shift and Bit Dependent Conditional Add Approach;2024 3rd International Conference on Artificial Intelligence For Internet of Things (AIIoT);2024-05-03