Design of Efficient Matrix Multiplication Processing Elements in Systolic Arrays using Shift and Bit Dependent Conditional Add Approach
Author:
Affiliation:
1. University of Cincinnati,Dept. of Engineering and Applied Science,Ohio,USA
2. Anurag University,Dept. of Electronics and Communication Engineering,Hyderabad,India
3. CVR College of Engineering,Dept. of Information Technology,Hyderabad,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10574534/10574536/10574675.pdf?arnumber=10574675
Reference14 articles.
1. Low-power multipliers by minimizing switching activities of partial products
2. Minimization of switching activities of partial products for designing low-power multipliers
3. BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture
4. High-performance low-power left-to-right array multiplier design
5. A Low-Power Multiplier With the Spurious Power Suppression Technique
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