Analytical modeling and evaluation of On-Chip Interconnects using Network Calculus
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/5066987/5071428/05071447.pdf?arnumber=5071447
Cited by 17 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
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3. A Study of Network-on-Chip Performance;2021 Thirteenth International Conference on Contemporary Computing (IC3-2021);2021-08-05
4. Design and Implementation of Argo NI-NoC Micro-architecture for MPSoC Using GALS Architecture;Lecture Notes in Electrical Engineering;2019-09-25
5. Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2016-02
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