Scaling Challenges for the Cross-Point Resistive Memory Array to Sub-10nm Node - An Interconnect Perspective-Reference-Cited by-同舟云学术

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Scaling Challenges for the Cross-Point Resistive Memory Array to Sub-10nm Node - An Interconnect Perspective

Published:2012-05 Issue: Volume: Page:
ISSN:
Container-title:2012 4th IEEE International Memory Workshop
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Author:

Liang Jiale,Yeh Stanley,Wong S. Simon,Wong H.-S. Philip

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6213613/6213616/06213650.pdf?arnumber=6213650

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Heterogeneous Instruction Set Architecture for RRAM-enabled In-memory Computing;Proceedings of the 18th ACM International Symposium on Nanoscale Architectures;2023-12-18

2. Memristor crossbar arrays with 6-nm half-pitch and 2-nm critical dimension;Nature Nanotechnology;2018-11-12

3. Redox-based memristive metal-oxide devices;Metal Oxide-Based Thin Film Structures;2018

4. A Comprehensive Model for Write Disturbance in Resistive Memory Composed of Cross-Point Array;IEICE Transactions on Electronics;2017

5. An efficient method for evaluating RRAM crossbar array performance;Solid-State Electronics;2016-06

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