Author:
Bendre Varsha,Kureshi A.K.
Cited by
7 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design of PnR Flow For Block Level Chip for Optimizing Leakage Power;2024 Third International Conference on Intelligent Techniques in Control, Optimization and Signal Processing (INCOS);2024-03-14
2. Implementing Power and Performance Optimization Techniques on Wireless SoC Design at Synthesis;Lecture Notes in Networks and Systems;2024
3. A Literature Review: Different Leakage Reduction Techniques for CMOS circuits;2021 International Conference on Advancements in Electrical, Electronics, Communication, Computing and Automation (ICAECA);2021-10-08
4. Analysis and Comparison of Leakage Power Reduction Techniques for VLSI Design;2021 International Conference on Computer Communication and Informatics (ICCCI);2021-01-27
5. Radical low-slung influence 12-Bit SAR ADC;Materials Today: Proceedings;2021