Evaluating a New RRAM Manufacturing Test Strategy
Author:
Affiliation:
1. RWTH Aachen University,Chair of Integrated Digital Systems and Circuit Design - IDS,Germany
2. NXP Semiconductors,Germany
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10154476/10154477/10154503.pdf?arnumber=10154503
Reference17 articles.
1. Memristors: Devices, Models, and Applications [Scanning the Issue]
2. Defects, Fault Modeling, and Test Development Framework for RRAMs
3. Review of Manufacturing Process Defects and Their Effects on Memristive Devices
4. Testing Open Defects in Memristor-Based Memories
5. Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT
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1. Lifecycle Management of Emerging Memories;2024 IEEE European Test Symposium (ETS);2024-05-20
2. Analyzing the Use of Temperature to Facilitate Fault Propagation in ReRAMs;2024 IEEE 25th Latin American Test Symposium (LATS);2024-04-09
3. A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing;Journal of Electronic Testing;2024-03-23
4. Characterization and Test of Intermittent Over RESET in RRAMs;2023 IEEE 32nd Asian Test Symposium (ATS);2023-10-14
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