Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT
Author:
Affiliation:
1. TU Delft,Computer Engineering Laboratory,The Netherlands
2. IBM Thomas J. Watson Research Centre,USA
Funder
ECSEL Joint Undertaking
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9983856/9983857/09983865.pdf?arnumber=9983865
Reference38 articles.
1. Validating a DFT Strategy’s Detection Capability regarding Emerging Faults in RRAMs
2. Exploiting the switching dynamics of HfO2-based ReRAM devices for reliable analog memristive behavior
3. Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory
4. Redundancy, repair, and test features of a 90nm embedded SRAM generator
5. Logic operation-based DFT method and 1R memristive crossbar March-like test algorithm
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1. Online Detection of Unique Faults in RRAMs;2024 IEEE European Test Symposium (ETS);2024-05-20
2. A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing;Journal of Electronic Testing;2024-03-23
3. A Dynamic Testing Scheme for Resistive-Based Computation-In-Memory Architectures;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22
4. Energy-efficient Computation-In-Memory Architecture using Emerging Technologies;2023 International Conference on Microelectronics (ICM);2023-12-17
5. Device-Aware Test for Ion Depletion Defects in RRAMs;2023 IEEE International Test Conference (ITC);2023-10-07
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