Asymmetric Polarization Response of Electrons and Holes in Si FeFETs: Demonstration of Absolute Polarization Hysteresis Loop and Inversion Hole Density over 2×1013 cm−2
Author:
Funder
JSPS
JST
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9264988/9264985/09265015.pdf?arnumber=9265015
Cited by 15 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Role of Nitrogen in Suppressing Interfacial States Generation and Improving Endurance in Ferroelectric Field-Effect Transistors;IEEE Transactions on Electron Devices;2024-08
2. Understanding HZO Thickness Scaling in Si FeFETs: Low Operating Voltage, Fast Wake-Up, and Suppressed Charge Trapping;IEEE Transactions on Electron Devices;2024-06
3. Interfacial-Layer-Free Ge0.95Si0.05 Nanosheet FeFETs;IEEE Transactions on Electron Devices;2024-03
4. Understanding memory window of ferroelectric field-effect transistor under coexistence of charge trapping and ferroelectric polarization: violation of linear superposition;Japanese Journal of Applied Physics;2024-01-10
5. Charge trapping effect at the interface of ferroelectric/interlayer in the ferroelectric field effect transistor gate stack;Chinese Physics B;2023-07-01
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