Charge trapping effect at the interface of ferroelectric/interlayer in the ferroelectric field effect transistor gate stack

Abstract

We study the charge trapping phenomenon that restricts the endurance of n-type ferroelectric field-effect transistors (FeFETs) with metal/ferroelectric/interlayer/Si (MFIS) gate stack structure. In order to explore the physical mechanism of the endurance failure caused by the charge trapping effect, we first establish a model to simulate the electron trapping behavior in n-type Si FeFET. The model is based on the quantum mechanical electron tunneling theory. And then, we use the pulsed I d–V g method to measure the threshold voltage shift between the rising edges and falling edges of the FeFET. Our model fits the experimental data well. By fitting the model with the experimental data, we get the following conclusions. (i) During the positive operation pulse, electrons in the Si substrate are mainly trapped at the interface between the ferroelectric (FE) layer and interlayer (IL) of the FeFET gate stack by inelastic trap-assisted tunneling. (ii) Based on our model, we can get the number of electrons trapped into the gate stack during the positive operation pulse. (iii) The model can be used to evaluate trap parameters, which will help us to further understand the fatigue mechanism of FeFET.