Write buffer design for on-chip cache

Author:

Chu P.P.,Gottipati R.

Publisher

IEEE Comput. Soc. Press

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. MC-ELMM: Multi-Chip Endurance-Limited Memory Management;Proceedings of the International Symposium on Memory Systems;2023-10-02

2. Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy;IEEE Transactions on Circuits and Systems I: Regular Papers;2020-01

3. Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2016-03

4. Secondary Bus Performance in Retiring Cache Write-Backs to Memory;Computer and Information Sciences II;2011

5. Intelligent Traffic Control System Based on DSP and Nios II;2009 International Asia Conference on Informatics in Control, Automation and Robotics;2009-02

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