Secondary Bus Performance in Retiring Cache Write-Backs to Memory

Author:

O’Farrell John W.,Venkatesh Rakshith Thambehalli,Baskiyar Sanjeev

Publisher

Springer London

Reference14 articles.

1. Moore, G.E.: Cramming more components onto integrated circuits. Electronics 38, 114–117 (1965)

2. Chu, P.P., Gottipati, R.: Write buffer design for on-chip cache. In: Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 311–316 (1994)

3. Baskiyar S, Wang, C.: A secondary channel between cache and memory for decreasing queuing delay. US provisional patent application no 61/003:542 (2007)

4. O’Farrell, J., Baskiyar S.: Improved real-time performance using a secondary bus. In: ISCA Proceedings of Computers and Their Applications, Honolulu, (2010)

5. The Essentials of the Intel Quickpath Architecture, Online. Available: http://www.intel.com/intelpress/files/Intel%28r%29_QuickPath_Interconnect_Electrial_Architecture.pdf

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