A 65 nm-node CMOS technology with highly reliable triple gate oxide suitable for power-considered system-on-a-chip-Reference-Cited by-同舟云学术

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A 65 nm-node CMOS technology with highly reliable triple gate oxide suitable for power-considered system-on-a-chip

Published: Issue: Volume: Page:
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Container-title:2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407)
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Author:

Fukai T.,Nakahara Y.,Terai M.,Koyama S.,Morikuni Y.,Suzuki T.,Nagase M.,Mineji A.,Matsuda T.,Tamura T.,Koba F.,Onoda T.,Yamada Y.,Komori M.,Kojima Y.,Yama Y.,Ikeda M.,Kudoh T.,Yamamoto T.,Imai K.

Publisher

Japan Soc. Applied Phys

Link

http://xplorestaging.ieee.org/ielx5/8657/27436/01221097.pdf?arnumber=1221097

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Clamping Diode-based Radiation Tolerant Circuit Design Approach;Analysis and Design of Resilient VLSI Circuits;2009-09-21

2. 3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits;Analysis and Design of Resilient VLSI Circuits;2009-09-21

3. Fringing Electric Field Effect on 65-nm-Node Fully Depleted Silicon-on-Insulator Devices;Japanese Journal of Applied Physics;2006-09-07

4. Novel polysilicon gate engineering with a laser thermal process for sub-40 nm CMOS devices;Solid-State Electronics;2004-10

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