Novel polysilicon gate engineering with a laser thermal process for sub-40 nm CMOS devices-Reference-Cited by-同舟云学术

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Novel polysilicon gate engineering with a laser thermal process for sub-40 nm CMOS devices

Published:2004-10 Issue:10-11 Volume:48 Page:1837-1842
ISSN:0038-1101
Container-title:Solid-State Electronics
language:en
Short-container-title:Solid-State Electronics

Author:

Yamamoto T.,Okabe K.,Kubo T.,Goto K.,Morioka H.,Wang Y.,Lin T.,Talwar S.,Kase M.,Sugii T.

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference9 articles.

1. Fukai T, Nakamura Y, Terai M, Koyama S, Morikuni Y, Suzuki T, et al. Symposium on VLSI Technology 2003. p. 83–4

2. Seibel C, Talwar S. US Patent 20030045074

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Gate Engineering to Improve Effective Resistance of 28-nm High- $k$ Metal Gate CMOS Devices;IEEE Transactions on Electron Devices;2016-01

2. Incorporation of tin in boron doped silicon for reduced deactivation of boron during post-laser-anneal rapid thermal processing;Journal of Applied Physics;2007-11

3. Suppression of Gate Depletion in p+-Polysilicon-Gated Sub-40 nm pMOSFETs by Laser Thermal Processing;Japanese Journal of Applied Physics;2005-04-21

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