Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire Technology-Reference-Cited by-同舟云学术

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Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire Technology

Published:2018-06 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE Symposium on VLSI Technology
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Author:

Hellings G.,Mertens H.,Subirats A.,Simoen E.,Schram T.,Ragnarsson L.-A.,Simicic M.,Chen S.-H.,Parvais B.,Boudier D.,Cretu B.,Machillot J.,Pena V.,Sun S.,Yoshida N.,Kim N.,Mocuta A.,Linten D.,Horiguchi N.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8481640/8510617/08510654.pdf?arnumber=8510654

Cited by 19 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Efficient and Accurate DTCO Simulation Framework for Reliability and Variability-Aware Explorations of FinFETs, Nanosheets, and Beyond;2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2024-03-03

2. Hybrid Integration of Gate-All-Around Stacked Si Nanosheet FET and Si/SiGe Super-Lattice FinFET to Optimize 6T-SRAM for N3 Node and Beyond;IEEE Transactions on Electron Devices;2024-03

3. SiGe/Si Superlattice Ferroelectric HfZrO₂ ΩFET and CMOS Inverter With SS_min,n = 62.4 mV/dec, I_ON/I_OFF > 1.0 × 10⁷, and Voltage Gain = 111.4 V/V;IEEE Electron Device Letters;2024-02

4. A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology;IEEE Journal of Solid-State Circuits;2024

5. A Low-Temperature SiO2 Interfacial Layer Preparation using Rapid Thermal Oxidation Process for GAA Nanosheet Based I/O Transistor;Silicon;2023-11-29

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