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A Low-Temperature SiO2 Interfacial Layer Preparation using Rapid Thermal Oxidation Process for GAA Nanosheet Based I/O Transistor

  • Published:2023-11-29 Issue: Volume: Page:
  • ISSN:1876-990X
  • Container-title:Silicon
  • language:en
  • Short-container-title:Silicon

Author:

Luo Huaizhi,Li Yan,Zhao Fei,Zhang Xi,Wang Shengkai,Xiong Wenjun,Mao Xiaotong,Li Yongliang

Funder

Strategic Priority Research Program of Chinese Academy of Sciences

Publisher

Springer Science and Business Media LLC

Subject

Electronic, Optical and Magnetic Materials

Reference21 articles.

1. Loubet N, Hook T, Montanini P, Yeung CW, Kanakasabapathy S, Guillom M, Yamashita T, Zhang J, Miao X, Wang J, Young A, Chao R, Kang M, Liu Z, Fan S, Hamieh B, Sieg S, Mignot Y, Xu W, Seo SC, Yoo J, Mochizuki S, Sankarapandian M, Kwon O, Carr A, Greene A, Park Y, Frougier J, Galatage R, Bao R, Shearer J, Conti R, Song H, Lee D, Kong D, Xu Y, Arceo A, Bi Z, Xu P, Muthinti R, Li J, Wong R, Brown D, Oldiges P, Robison R, Arnold J, Felix N, Skordas S, Gaudiello J, Standaert T, Jagannathan H, Corliss D, Na MH, Knorr A, Wu T, Gupta D, Lian S, Divakaruni R, Gow T, Labelle C, Lee S, Paruchuri V, Bu H, Khare M (2017) Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. 2017 symposium on VLSI technology, pp T230–T231

2. Mertens H, Ritzenthaler R, Pena V, Santoro G, Kenis K, Schulze A, Litta ED, Chew SA, Devriendt K, Demuynck CrS, Yakimets D, Jang D, Spessot A, Eneman G, Dangol A, Lagrain P, Bender H, Sun S, Korolik M, Kioussis D, Kim M, Bu KH, Chen SC, Cogorno M, Devrajan J, Machillot J, Yoshida N, Kim N, Barla K, Mocuta D, Horiguchi N (2017) Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration. In: 2017 IEEE international electron devices meeting (IEDM), pp 37.4.1–37.4.4

3. Bae G, Bae DI, Kang M, Hwang SM, Kim SS, Seo B, Kwon TY, Lee TJ, Moon C, Choi YM, Oikawa K, Masuoka S, Chun KY, Park SH, Shin HJ, Kim JC, Bhuwalka KK, Kim DH, Kim WJ, Yoo J, Jeon HY, Yang MS, Chung SJ, Kim D, Ham BH, Park KJ, Kim WD, Park SH, Song G, Kim YH, Kang MS, Hwang KH, Park CH, Lee JH, Kim DW, Jung SM, Kang HK (2018) 3nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications. 2018 IEEE international electron devices meeting (IEDM), pp 28.7.1–28.7.4

4. Cheng X, Li Y, Zhao F, Chen A, Liu H, Li C, Zhang Q, Yin H, Luo J, Wang W (2022) 4-Levels vertically stacked SiGe channel nanowires gate-all-around transistor with novel channel releasing and source and drain silicide process. Nanomaterials 12(5):889

5. Saleh R, Wilton S, Mirabbasi S, Hu A, Greenstreet M, Lemieux G, Pande PP, Grecu C, Ivanov A (2006) System-on-Chip: reuse and integration. Proc IEEE 94(6):1050–1069
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