A High Speed FPGA Implementation of a 1024-Point Complex FFT Processor
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/5473909/5474422/05474485.pdf?arnumber=5474485
Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. An Architecture for On board Frequency Domain Analysis of Launch Vehicle Vibration Signals;Defence Science Journal;2023-03-13
2. Design optimisation of multiplier‐free parallel pipelined FFT on field programmable gate array;IET Circuits, Devices & Systems;2020-10
3. Hardware accelerated range Doppler algorithm for SAR data processing using Zynq processor;Circuit World;2020-07-15
4. Low cost, faster detection of cognitive radio through filter banks with bandpass sampling;Physical Communication;2019-04
5. An Efficient Pipelined Feedback Processor for Computing a 1024-Point FFT Using Distributed Logic;Advances in Intelligent Systems and Computing;2018-08-23
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