Design optimisation of multiplier‐free parallel pipelined FFT on field programmable gate array
Author:
Affiliation:
1. Electronics and Communication EngineeringJawaharlal Nehru Technological UniversityKakinadaIndia
2. Electronics and Communication EngineeringShri Vishnu Engineering College for Women AutonomousBhimavaramIndia
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Control and Systems Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2019.0512
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4. Derafshi Z.H. Frounchi J. Taghipour H.: ‘A high speed FPGA implementation of a 1024‐point complex FFT processor’.2010 Second Int. Conf. on Computer and Network Technology Bangkok Thailand 2010 doi:10.1109/iccnt.2010.12
5. He H. Guo H.: ‘The realization of FFT algorithm based on FPGA co‐processor’.2008 Second Int. Symp. on Intelligent Information Technology Application Los Alamitos CA USA 2008 doi:10.1109/iita.2008.461
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