Primitive path delay faults: identification and their use in timing analysis-Reference-Cited by-同舟云学术

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Primitive path delay faults: identification and their use in timing analysis

Published:2000 Issue:11 Volume:19 Page:1347-1362
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Sivaraman M.,Strojwas A.J.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/19328/00892858.pdf?arnumber=892858

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Analysis of Quarter Method Applied ROM-Based DDFS Architecture;IEEE Access;2023

2. Fast identification of true critical paths in sequential circuits;Microelectronics Reliability;2018-02

3. Non-enumerative Generation of Path Delay Distributions and Its Application to Critical Path Selection;ACM Transactions on Design Automation of Electronic Systems;2016-12-28

4. On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation;Journal of Electronic Testing;2008-01-08

5. Implicit Critical PDF Test Generation with Maximal Test Efficiency;2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems;2006-10

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