Non-enumerative Generation of Path Delay Distributions and Its Application to Critical Path Selection

Author:

Somashekar Ahish Mysore1,Tragoudas Spyros1,Jayabharathi Rathish2,Gangadhar Sreenivas3

Affiliation:

1. Southern Illinois University, Carbondale, IL

2. Intel Corporation, Folsom, CA

3. Intel Corporation, Austin, TX

Abstract

A Monte Carlo-based approach is proposed capable of identifying in a non-enumerative and scalable manner the distributions that describe the delay of every path in a combinational circuit. Furthermore, a scalable approach to select critical paths from a potentially exponential number of path candidates is presented. Paths and their delay distributions are stored in Zero Suppressed Binary Decision Diagrams. Experimental results on some of the largest ISCAS-89 and ITC-99 benchmarks shows that the proposed method is highly scalable and effective.

Funder

NSF I/UCRC for Embedded Systems at SIUC

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Cross-level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors;ACM Transactions on Design Automation of Electronic Systems;2019-05-31

2. Efficient Critical Path Selection Under a Probabilistic Delay Model;Proceedings of the on Great Lakes Symposium on VLSI 2017;2017-05-10

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