Analysis of Quarter Method Applied ROM-Based DDFS Architecture
Author:
Affiliation:
1. Department of Electronic Engineering, Seoul National University of Science and Technology, Seoul, Republic of Korea
Funder
National Research Foundation of Korea
Institute for Information & Communications Technology Planning & Evaluation
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/6287639/10005208/10287945.pdf?arnumber=10287945
Reference33 articles.
1. Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter
2. Direct Digital Synthesizer With Sine-Weighted DAC at 32-GHz Clock Frequency in InP DHBT Technology
3. Reducing Lookup-Table Size in Direct Digital Frequency Synthesizers Using Optimized Multipartite Table Method
4. Phase-Adjustable Pipelining ROM-Less Direct Digital Frequency Synthesizer With a 41.66-MHz Output Frequency
5. Primitive path delay faults: identification and their use in timing analysis
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