Phase-Adjustable Pipelining ROM-Less Direct Digital Frequency Synthesizer With a 41.66-MHz Output Frequency

Author:

Wang C.-C.,Huang J.-M.,Tseng Y.-L.,Lin W.-J.,Hu R.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Signal Processing

Cited by 20 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Programmable Square-Wave Delay Circuit with Self-Calibration Structure;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20

2. Analysis of Quarter Method Applied ROM-Based DDFS Architecture;IEEE Access;2023

3. Phase to Amplitude Converter;High-Speed and High-Performance Direct Digital Frequency Synthesizer Design;2022

4. A High-Frequency Digital Computational Synthesizer of Composite Broadband Signals for Telecommunication Systems;Instruments and Experimental Techniques;2021-07

5. A Memory-Based Direct-Digital Frequency Synthesizer for Fractional Synchronization;IEEE Transactions on Circuits and Systems II: Express Briefs;2021

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